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march 1996 ndC7001C dual n & p -channel enhancement mode field effect transistor general description features __ __________________________________________________________________________________________ absolute maximum ratings t a = 25c unless otherwise noted symbol parameter n-channel p-channel units v dss drain-source voltage 50 -50 v v gss gate-source voltage - continuous 20 -20 v i d drain current - continuous (note 1a) 0.51 -0.34 a - pulsed 1.5 -1 p d maximum power dissipation (note 1a) 0.96 w (n ote 1b) 0.9 (no te 1c) 0.7 t j ,t stg operating and storage temperature range -55 to 15 0 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 130 c/w r q jc thermal resistance, junction-to-case (note 1) 60 c/w ndC7001C.sam these dual n and p-channel enhancement mode power field effect transistors are produced using fairchild's proprietary, high cell density, dmos technology. this very high density process has been designed to minimize on-state resistance, provide rugged and reliable performance and fast switching. these devices is particularly suited for low voltage, low current, switching, and power supply applications . n-channel 0.51 a, 50v, r ds(on) = 2 w @ v gs =10v p-channel -0.34a, -50v. r ds(on ) = 5 w @ v gs =-10v. high density cell design for low r ds(on) . proprietary supersot tm -6 package design using copper lead frame for superior thermal and electrical capabilities. high saturation current . 1 5 4 6 3 2 supersot tm -6 ? 1997 fairchild semiconductor corporation
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions type min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a n-ch 50 v v gs = 0 v, i d = -250 a p-ch -50 i dss zero gate voltage drain current v ds = 40 v , v gs = 0 v n-ch 1 a t j = 12 5c 500 v ds = -40 v, v gs = 0 v p-ch -1 t j = 12 5c -500 i gssf gate - body leakage, forward v gs = 20 v, v ds = 0 v all 100 na i gssr gate - body leakage, reverse v gs = -20 v, v ds = 0 v all -100 na on characteristics (note 2 ) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a n-ch 1 1.9 2.5 v t j = 12 5c 0.8 1.5 2.2 v ds = v gs , i d = -250 .a p-ch -1 -2.5 -3.5 t j = 12 5c -0.8 -2.2 -3 r ds(on) static drain-source on-resistance v gs = 10 v, i d = 0.51 a n-ch 1 2 w t j = 125c 1.7 3.5 v gs = 4.5 v, i d = 0.35 a 1.6 4 v gs = -10 v, i d = -0.34 a p-ch 2.5 5 t j = 125c 4 10 v gs = -4.5 v, i d = -0.25 a 5.3 7.5 i d (on) on-state drain current v gs = 10 v, v ds = 10 v n-ch 1.5 a v gs = -10 v, v ds = -10 v p-ch -1 g fs forward transconductance v ds = 10 v, i d = 0.51 a n-ch 400 ms v ds = -10 v, i d = -0.34 a p-ch 250 dynamic characteristics c iss input capacitance n-channel v ds = 25 v, v gs = 0 v, f = 1.0 mhz p-channel v ds = -25 v, v gs = 0 v, f = 1.0 mhz n-ch 20 pf p-ch 40 c oss output capacitance n-ch 13 pf p-ch 13 c rss reverse transfer capacitance n-ch 5 pf p-ch 4 ndC7001C.sam
electrical characteristics (t a = 25 o c unless otherwise noted) symbol parameters conditions type min typ max units switching ch aracteristics (note 2) t d(on) turn - on delay time n-channel v dd = 25 v, i d = 0.25 a , v gs = 10 v, r gen = 25 w p-channel v dd = -25 v, i d = -0.25 a , v gs = -10 v, r gen = 25 w n-ch 6 20 ns p-ch 14 20 t r turn - on rise time n-ch 6 20 p-ch 6 20 t d(off) turn - off delay time n-ch 11 20 p-ch 13 20 t f turn - off fall time n-ch 5 20 p-ch 6 20 q g total gate charge n-channel v ds = 25 v, i d = 0.51 a, v gs = 10 v p -channel v ds = -25 v, i d = -0.34 a, v gs = -10 v n-ch 1 nc p-ch 1.3 q gs gate-source charge n-ch 0.19 nc p-ch 0.23 q gd gate-drain charge n-ch 0.33 nc p-ch 0.38 drain-source diode characteristics i s maximum continuous source current n-ch 0.51 a p-ch -0.34 i sm maximum pulse source current (note 2) n-ch 1.5 a p-ch -1 v sd drain-source diode forward voltage v gs = 0 v, i s = 0.51 a (note 2) n-ch 0.8 1.2 v v gs = 0 v, i s = -0.34 a (note 2) p-ch -0.8 -1.2 notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. p d ( t ) = t j - t a r q j a ( t ) = t j - t a r q j c + r q c a ( t ) = i d 2 ( t ) r d s ( o n ) t j typical r q ja for single device operation using the board layouts shown below on 4.5"x5" fr-4 pcb in a still air environment : a. 130 o c/w when mounted on a 0.125 in 2 pad of 2oz cpper. b. 140 o c/w when mounted on a 0.005 in 2 pad of 2oz cpper. c. 180 o c/w when mounted on a 0.0015 in 2 pad of 2oz cpper. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. ndC7001C.sam 1a 1b 1c
ndC7001C.sam 0 1 2 3 4 5 0 0.3 0.6 0.9 1.2 1.5 v , drain-source voltage (v) i , drain-source current (a) 6.0 v =10v gs ds d 8.0 7.0 3.5 4.0 4.5 5.0 5.5 3.0 -50 -25 0 25 50 75 100 125 150 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 t , junction temperature (c) drain-source on-resistance j v = 10v gs i = 0.51a d r , normalized ds(on) -50 -25 0 25 50 75 100 125 150 0.7 0.8 0.9 1 1.1 1.2 t , junction temperature (c) gate-source threshold voltage j i = 250a d v = v ds gs v , normalized th 0 0.3 0.6 0.9 1.2 1.5 0.5 1 1.5 2 2.5 3 i , drain current (a) drain-source on-resistance d v = 3.5v gs r , normalized ds(on) 6.0 4.0 4.5 5.0 5.5 10 8.0 7.0 0 0.3 0.6 0.9 1.2 1.5 0.5 1 1.5 2 2.5 i , drain current (a) drain-source on-resistance t = 125c j 25c d v = 10v gs -55c r , normalized ds(on) typical electrical characteristics: n-channel figure 1. n-channel on-region characteristics. figure 2. n-channel on-resistance variation wit h gate voltage and drain current. figure 3. n-channel on-resistance variation with temperature. figure 4. n-channel on-resistance variation with drain current and temperature. figure 5. n-channel transfer characteristics. figure 6. n-channel gate threshold variation with temperature. 1 2 3 4 5 6 7 8 0 0.3 0.6 0.9 1.2 1.5 v , gate to source voltage (v) i , drain current (a) 25c 125c v = 10v ds gs d t = -55c j
ndC7001C.sam -50 -25 0 25 50 75 100 125 150 0.88 0.92 0.96 1 1.04 1.08 1.12 1.16 t , junction temperature (c) drain-source breakdown voltage i = 250a d bv , normalized dss j 0.2 0.4 0.6 0.8 1 1.2 0.001 0.01 0.1 0.5 1 1.5 v , body diode forward voltage (v) i , reverse drain current (a) t = 125c j 25c -55c v = 0v gs sd s 0 0.2 0.4 0.6 0.8 1 1.2 0 2 4 6 8 10 q , gate charge (nc) v , gate-source voltage (v) g gs i = 0.51a d v = 25v ds 0.1 0.2 0.5 1 2 5 10 20 50 1 2 5 10 20 50 100 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0v gs c oss c rss figure 7. n-channel breakdown voltage variation with temperature. figure 8. n-channel body diode forward voltage variation with current and temperature . figure 9. n-channel capacitance characteristics. figure 10. n-channel gate charge characteristics. typical electrical characteristics: n-channel (continued) 0 0.3 0.6 0.9 1.2 1.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 v , gate to source voltage (v) i , drain current (a) 25c 125c v = 10v ds gs d t = -55c j figure 11. n-channel transconductance variation with drain current and temperature.
ndC7001C.sam -6 -5 -4 -3 -2 -1 0 -1 -0.8 -0.6 -0.4 -0.2 v , drain-source voltage (v) i , drain-source current (a) -6.0 ds d v = -10v gs -9.0 -8.0 -5.0 -4.0 -7.0 -3.5 -50 -25 0 25 50 75 100 125 150 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 t , junction temperature (c) drain-source on-resistance j v = -10v gs i = -0.34a d r , normalized ds(on) -50 -25 0 25 50 75 100 125 150 0.8 0.85 0.9 0.95 1 1.05 1.1 t , junction temperature (c) gate-source threshold voltage j i = -250a d v = v ds gs v , normalized th -1 -0.8 -0.6 -0.4 -0.2 0.5 1 1.5 2 2.5 3 i , drain current (a) drain-source on-resistance v =-4.5v gs d -7.0 r , normalized ds(on) -6.0 -5.0 -10 -9.0 -8.0 -1 -0.8 -0.6 -0.4 -0.2 0.5 1 1.5 2 2.5 i , drain current (a) drain-source on-resistance d r , normalized ds(on) v =-10 v gs t = 125c j 25c -55c typical electrical characteristics: p-channel (continued) figure 12 . p-channel on-region characteristics. figure 13 . p-channel on-resistance variation wit h gate voltage and drain current. figure 14 . p-channel on-resistance variation with temperature. figure 15 . p-channel on-resistance variation with drain current and temperature. figure 16 . p-channel transfer characteristics. figure 17 . p-channel gate threshold variation with temperature. -8 -7 -6 -5 -4 -3 -2 -1 -1 -0.8 -0.6 -0.4 -0.2 v , gate to source voltage (v) i , drain current (a) 25c 125c v =- 10v ds gs d t = -55c j
ndC7001C.sam -50 -25 0 25 50 75 100 125 150 0.9 0.95 1 1.05 1.1 1.15 t , junction temperature (c) drain-source breakdown voltage i = 250a d bv , normalized dss j 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0.001 0.005 0.01 0.05 0.1 0.5 1 -v , body diode forward voltage (v) -i , reverse drain current (a) t = 125c j 25c -55c v =0v gs sd s 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -10 -8 -6 -4 -2 0 q , gate charge (nc) v , gate-source voltage (v) g gs -48 v = -12v ds i = -0.34a d -24 0.1 0.2 0.5 1 2 5 10 20 50 1 2 5 10 20 50 100 -v , drain to source voltage (v) capacitance (pf) ds f = 1 mhz v = 0v gs c oss c iss c rss figure 18 . p-channel breakdown voltage variation with temperature. figure 19 . p-channel body diode forward voltage variation with current and temperature . figure 20 . p-channel capacitance characteristics. figure 21 . p-channel gate charge characteristics. typical electrical characteristics: p-channel (continued) -1 -0.8 -0.6 -0.4 -0.2 0 0.1 0.2 0.3 0.4 0.5 i , drain current (a) g , transconductance (siemens) t = -55c j d fs v =- 10v ds 125c 25c figure 22 . p-channel transconductance variation with drain current and temperature.
ndC7001C.sam typical thermal characteristics: n & p-channel 0 0.2 0.4 0.6 0.8 1 0.6 0.7 0.8 0.9 1 1.1 1.2 2oz copper mounting pad area (in ) steady-state power dissipation (w) 2 1c 1b 1a 4.5"x5" fr-4 board t = 25 c still air a o 0 0.025 0.05 0.075 0.1 0.125 0.35 0.4 0.45 0.5 0.55 2oz copper mounting pad area (in ) i , steady-state drain current (a) 2 1c 1b 1a 4.5"x5" fr-4 board t = 25 c still air v = 10v a o gs d figure 24 . n-ch maximum steady-state drain current versus copper mounting pad area. figure 23 . sot-6 dual package maximum steady-state power dissipation versus copper mounting pad area. 0 0.025 0.05 0.075 0.1 0.125 0.2 0.25 0.3 0.35 0.4 2oz copper mounting pad area (in ) -i , steady-state drain current (a) 2 1c 1b 1a 4.5"x5" fr-4 board t = 25 c still air v = -10v a o gs d figure 25 . p-ch maximum steady-state drain current versus copper mounting pad area. 1 2 5 10 20 50 70 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 v , drain-source voltage (v) i , drain current (a) ds d rds(on) limit v = 10v single pulse r = see note 1c t = 25c gs a q ja 1s 100ms 100us dc 10ms 1ms figure 26 . n-channel maximum safe operating area. 1 2 5 10 20 50 70 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 -v , drain-source voltage (v) -i , drain current (a) ds d rds(on) limit v = -10v single pulse r = see note 1c t = 25c gs a q ja 1s 100ms 100us dc 10ms 1ms figure 27 . p-channel maximum safe operating area .
ndC7001C.sam g d s v dd r l v v in out v gs dut r gen 10% 50% 90% 10% 90% 90% 50% v in v out on off d(off) f r d(on) t t t t t t 10% pulse width figure 29 . n or p-channel switching test circuit . figure 30 . n or p-channel switching waveforms . typical thermal characteristics: n & p-channel 0.0001 0.001 0.01 0.1 1 10 100 300 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 r(t), normalized effective duty cycle, d = t / t 1 2 r (t) = r(t) * r r = see note 1c q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2 figure 28 . transient thermal response curve . note: thermal characterization performed using the conditions described in note 1c. transient thermal response will change depending on the circuit board design.
1998 fairchild semiconductor corporation embossed carrier tape ssot-6 packaging configuration: fi g ur e 1.0 comp onent s lead er tape 500mm mi nimum or 125 emp t y poc kets traile r tap e 300mm mi nimum or 75 empt y poc kets ssot-6 tape leader and trailer configuration: fi g ur e 2.0 cover tape carrier tape note/comments packaging option ssot-6 packaging information stan da rd (no f l ow c ode ) d87z packaging type reel size tnr 7" di a tnr 13" qty per reel/tube/bag 3,000 10,000 box dimension (mm) 184x 187x 47 343x 343x 64 max qty per box 9,000 30,000 weight per unit (gm) 0.0158 0.0158 weight per reel (kg) 0.1440 0.4700 f63tnr label customize label antistatic cover tape 184mm x 187mm x 47mm pizza box fo r standar d option f63tnr label f63tnr label f63tnr label sampl e 343mm x 342mm x 64mm intermediate box fo r d87z option f63tnr label ssot-6 unit orientation 631 631 631 631 631 pin 1 lot: cbvk741b019 fsid: fdc633n d/c1: d9842 qty1: spec rev: spec: qty: 3000 d/c2: qty2: cpn: n/f: f (f63tnr)3 packaging description: ssot-6 parts are shipped in tape. the carrier tape is made from a dissipative (carbon filled) polycarbonate resin. the cover tape is a multilayer film (heat activated adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. these reeled parts in standard option are shipped with 3,000 units per 7" or 177cm diameter reel. the reels are dark blue in color and is made of polystyrene plastic (anti- static coated). other option comes in 10,000 units per 13" or 330cm diameter reel. this and some other options are described in the packaging information table. these full reels are individually barcode labeled and placed inside a pizza box (illustrated in figure 1.0) made of recyclable corrugated brown paper with a fairchild logo printing. one pizza box contains three reels maximum. and these pizza boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped. supersot tm -6 tape and reel data and package dimensions august 1999, rev. c
p1 a0 d1 p0 f w e1 d0 e2 b0 tc wc k0 t dimensions are in inches and millimeters tape size reel option dim a dim b dim c dim d dim n dim w1 dim w2 dim w3 (lsl-usl) 8mm 7" dia 7.00 177.8 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 2.165 55 0.331 +0.059/-0.000 8.4 +1.5/0 0.567 14.4 0.311 0.429 7.9 ?10.9 8mm 13" dia 13.00 330 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 4.00 100 0.331 +0.059/-0.000 8.4 +1.5/0 0.567 14.4 0.311 0.429 7.9 ?10.9 see detail aa dim a max 13" diameter option 7" diameter option dim a max see detail aa w3 w2 max measured at hub w1 measured at hub dim n dim d min dim c b min detail aa notes: a0, b0, and k0 dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). 20 deg maximum component rotation 0.5mm maximum 0.5mm maximum sketch c (top view) component lateral movement typical component cavity center line 20 deg maximum typical component center line b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation user direction of feed ssot-6 embossed carrier tape configuration: fi g ure 3.0 ssot-6 reel configuration: fi g ure 4.0 dimensions are in millimeter pkg type a0 b0 w d0 d1 e1 e2 f p1 p0 k0 t wc tc ssot-6 (8mm) 3.23 +/-0.10 3.18 +/-0.10 8.0 +/-0.3 1.55 +/-0.05 1.125 +/-0.125 1.75 +/-0.10 6.25 min 3.50 +/-0.05 4.0 +/-0.1 4.0 +/-0.1 1.37 +/-0.10 0.255 +/-0.150 5.2 +/-0.3 0.06 +/-0.02 supersot tm -6 tape and reel data and package dimensions, continued july 1999, rev. c
1998 fairchild semiconductor corporation supersot -6 (fs pkg code 31, 33) supersot tm -6 tape and reel data and package dimensions, continued september 1998, rev. a 1:1 scale 1:1 on letter size paper dimensions shown below are in: inches [millimeters] part weight per unit (gram): 0.0158
trademarks acex? coolfet? crossvolt? e 2 cmos tm fact? fact quiet series? fast ? fastr? gto? hisec? the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. syncfet? tinylogic? uhc? vcx? isoplanar? microwire? pop? powertrench qfet? qs? quiet series? supersot?-3 supersot?-6 supersot?-8 ? rev. d

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